699 F.2d 1325
216 U.S.P.Q. 1033
Ingrid E. MAGDO and Steven Magdo, Appellants,v.Else KOOI, Appellee.Ingrid E. MAGDO and Steven Magdo, Appellants,v.Douglas L. PELTZER, Appellee.Ingrid E. MAGDO and Steven Magdo, Appellants-Cross-Appellees,v.Else KOOI, Appellee-Cross-Appellant,v.Douglas L. PELTZER, Appellee-Cross-Appellee.
Nos. 82-550 to 82-553.
United States Court of Appeals,Federal Circuit.
Feb. 14, 1983.

Robert J. Haase, Hopwell Junction, N.Y., argued, for Ingrid E. Magdo and Steven Magdo.  With him on the briefs were Darryl Mexic and Sughrue, Mion, Zinn, Macpeak & Seas, Washington, D.C.
Alan H. MacPherson, San Francisco, Cal., argued, for Douglas L. Peltzer.  With him on the briefs were Skjerven, Morrill, MacPherson & Drucker, San Francisco, Cal.
Jack Oisher, argued, for Else Kooi.  With him on the briefs was Steven R. Biren, Tarrytown, N.Y.
Before DAVIS, BENNETT and NIES, Circuit Judges.
NIES, Circuit Judge.


1
These four consolidated appeals under 35 U.S.C. Sec. 141 (1976) arose out of three interferences in which the Patent and Trademark Office Board of Patent Interferences (board) awarded priority to Douglas L. Peltzer (Peltzer) in Interference Nos. 98,427 and 98,428 and to Else Kooi (Kooi) in Interference No. 99,248.  Ingrid E. Magdo and Steven Magdo (the Magdos) appeal from the awards of priority in all three interferences;  Kooi (designated as cross-appellant) appeals from the award of priority in Interference No. 98,427.

The appeals raise the following issues:

2
(1) whether the board correctly found that the Magdos did not prove conception of the inventions of the counts;  and


3
(2) whether Peltzer may not be awarded priority because of asserted defects in the disclosure set forth in his specification or because of an asserted concession of priority resulting from a disclaimer filed in one of the interferences.


4
We affirm the respective awards of priority made by the board.

The Status of the Parties

5
The Magdos are a party to all three interferences on the basis of a single application filed September 20, 1972 (Magdo application)1 which was accorded the benefit of an earlier application filed June 7, 1971.2


6
Kooi is a party in Interference Nos. 98,427 and 99,248 on the basis of a single application (Kooi application).3   The Kooi application was filed July 8, 1971, and was accorded the benefit of a Dutch application4 filed July 10, 1970.


7
Peltzer is a party in Interference Nos. 98,427 and 98,428 on the basis of United States Patent No. 3,648,125 ("Peltzer patent") which issued on an application filed February 2, 1971 ("original application").5


8
Prior to the issuance of his patent, Peltzer had filed a divisional application6 based on his original application.  That divisional application was followed by a continuation application.7   Interference No. 99,248 was instituted between the Magdo application, the Kooi application, and the Peltzer continuation application after Peltzer and Kooi copied a count proposed by Magdo.  During this proceeding, Peltzer filed a disclaimer of the subject matter of the count.  As a consequence, Peltzer was adjudged not the first inventor of the subject matter in issue therein and Interference No. 99,248 was terminated as to him.

The Counts

9
The counts in all three interferences relate to an improvement in a feature critical to proper operation of integrated circuits (IC's).  IC's are comprised of a plurality of circuit elements formed within and on the surface of a semiconductor material, e.g., silicon.  Because the silicon can conduct electricity, various circuit elements formed in the silicon must be electrically isolated from one another.  The prior method of isolation is displayed in these cross-sections of an IC before and after the step of diffusing p-type isolation regions through an n-type upper layer of silicon to a lower p-type layer:NOTE: OPINION CONTAINS TABLE OR OTHER DATA THAT IS NOT VIEWABLE


10
The n-type "isolation islands" are electrically isolated from each other by sidewalls C2  creating what is termed back to back "PN junctions."    The various circuit elements, e.g., resistors, diodes, and transistors, are formed in the isolation islands during subsequent processing steps.8   This form of isolation results in a substantial amount of area between isolation islands being wasted, area that would otherwise be available for circuit elements.  The counts are directed to a form of electrical isolation which requires less between-island's area by replacing the back to back PN junctions with sidewalls of silicon dioxide (oxide) and adding a PN junction floor.


11
The electrical isolation defined by the counts9 of these interferences is now known in the industry as the Fairchild Isoplanar II process.10   We will limit our discussion to certain fundamental features which are common to all of the counts and around which the disputes, as presented on appeal, center.


12
The IC involved herein is composed of a silicon layer referred to as a substrate.  On the surface of this substrate is grown, in a proper atmosphere, a second silicon layer whose crystalline structure is the same as that of the substrate.  This second layer is referred to as the epitaxial layer, or epi.  Prior to growing the epi, a layer of opposite type is diffused into the substrate (e.g., if the substrate is p-type, the diffused layer is n-type).  The epi, which is grown over both the substrate and the diffused layer, sandwiches the diffused layer between the epi and the substrate thus creating a buried layer.  The buried layer-substrate boundary forms a lateral PN junction which acts as an electrical barrier between the epi and substrate:


13
NOTE: OPINION CONTAINS TABLE OR OTHER DATA THAT IS NOT VIEWABLE


14
The epi layer is divided into portions or "pockets" around which annular-shaped regions of oxide (SiO2 ) are formed.  The oxide regions reach into the epi11 and extend from the top surface of the epi to the bottom surface along which the lateral PN junction lies:


15
NOTE: OPINION CONTAINS TABLE OR OTHER DATA THAT IS NOT VIEWABLE


16
The result of the oxide reaching from the surface to the lateral PN junction is to create an electrically isolating "wall" and "floor" around the pockets where the circuit elements are to be formed.  Thus, the pockets, and, necessarily, the circuit elements contained therein, are isolated from one another.

The Magdos' Case for Conception

17
The board's opinion in Interference No. 98,427 is published at 212 USPQ 831 and what was said there with respect to the Magdos appears verbatim in the board's opinions in the other two interferences and will not be repeated here.  The Magdos relied before the board, and again before this court, upon a portion of an exhibit, reproduced at 212 USPQ at 834, which exhibit is illustrative of all of the Magdo's proofs with respect to their conception and reduction to practice.


18
The board held that that exhibit shows a device wherein the oxide extends from the surface of a top epi layer to a PN junction that is formed vertically within a second epi layer, and that the vertical PN junction contacts the lateral PN junction.  Thus, the board held that the oxide does not extend through the epi to a lateral PN junction, but rather contacts the lateral PN junction via another PN junction.  The board held that the exhibit did not satisfy the counts and, accordingly, that the Magdos had failed to establish conception and reduction to practice.  We agree.


19
The Magdo's argue strenuously that the board failed to recognize that the two epitaxial layers depicted in the exhibit can be treated as one.  However, the board's discussion of the presence of more than one epi layer must be read in context.  The board held that the oxide must extend "through 'said epitaxial layer,' i.e., the epitaxial layer overlying and contiguous with the substrate".  212 USPQ at 835 (emphasis deleted).  Thus, irrespective of the number of layers of which the epi may be composed, the oxide must extend from the epi's top surface until it contacts the PN junction that lies substantially along the epi-substrate interface.  While there is a statement in Peltzer's patent that the lateral PN junction can be comprised of more than one junction, that teaching is directed to adjoining horizontal PN junctions and cannot be read as providing for a PN junction which extends upwards into the area between circuit elements.  Indeed, the invention was aimed at eliminating the use of PN junctions between circuit elements for electrical isolation.  Yet, Ingrid Magdo, a co-inventor, testified that PN junctions were the primary form of isolation in their device, whereas the oxide provided isolation "on the surface."    As the Magdos' device necessarily involves PN junctions between circuit elements rather than oxide, we conclude that the board did not err in holding that, in each interference, the Magdos had failed to establish conception or reduction to practice of the invention of the counts.

Peltzer's Case for Conception

20
The board held that Peltzer had proven conception by January 1970, coupled with diligence to his filing date, and had priority, therefore, over both the Magdos and Kooi.  Kooi had introduced no evidence supporting a date earlier than Peltzer's.  On appeal, Peltzer's proof of conception by January 1970 is not challenged.

Disclaimer

21
Peltzer's participation in Interference Nos. 98,427 and 98,428 is challenged in view of Peltzer's disclaimer in Interference No. 99,248.  We agree with the board that Peltzer's disclaimer does not effect a disclaimer of the counts in these interferences, cf. Hartford-Empire Co. v. Hazel-Atlas Glass Co., 59 F.2d 399, 412-13 (CA 3 1932), and cases cited (a disclaimer extends only to the particular claims involved and does not affect any other claims), or in any other way result in a concession of priority in the other interferences.  We do not see that it would serve any useful purpose to elaborate on the board's treatment of an issue we find unsupported by the facts and wholly without merit.

Best Mode

22
Both the Magdos and Kooi contend, but originally for different reasons, that priority may not be awarded to Peltzer because the quality of Peltzer's disclosure is so poor as to effectively result in concealment of his best mode contrary to the requirements of 35 U.S.C. Sec. 112, first paragraph.12

A.

23
Kooi did not raise this issue, or a further contention that Peltzer's disclosure was not enabling, during the motions period, and did not articulate the specific grounds for such challenges until well after the testimony period had ended.  At that time it became clear that both attacks were premised on the identical alleged deficiency, namely:


24
The specification calls for thin epitaxial layers yet does not disclose any method for making thin epitaxial layers.


25
We conclude that a challenge on this basis, however formalized, was untimely.


26
The basis for the asserted attack was easily known from a simple reading of Peltzer's patent.  Adding that the failure to disclose "how to make" the layers thin is also a failure to disclose "best mode" does not change the nature of the accusation.   Department of Energy v. Daugherty, 687 F.2d 438, 215 USPQ 4 (Cust & Pat.App.1982).  In essence, Kooi's assertions can be distilled to one issue, namely, that Peltzer's patent lacks an enabling disclosure.  Such a challenge was clearly tardy and the board properly disregarded it.

B.

27
A second alleged deficiency is that Peltzer knew that his devices could suffer from a phenomenon known as "channeling,"13 yet he failed to disclose the problem or a solution.  That set of facts is asserted to amount to a failure to disclose best mode.  The board originally declined to consider this issue, as such, holding that a best mode challenge was not an issue ancillary to priority.


28
From the same set of facts the board was asked, alternatively, to conclude that Peltzer's conception of the invention was not complete because Peltzer did not show that he had also conceived a solution to channeling.  The board viewed this argument as an attack on the Peltzer disclosure as "inoperative" under the guise of "lack of conception."    No motion to dissolve for inoperability had been filed, and since the Magdos conceded they had long known of channeling and its solution, the board concluded that it "would be inimical to the interest of orderly procedure" to permit a late challenge to operability.  212 USPQ at 837.  In any event, the board held that the Magdos did not sustain their burden of proof on inoperability.


29
After the decision of the United States Court of Customs and Patent Appeals in Tofe v. Winchell, 645 F.2d 58, 209 USPQ 379 (Cust. & Pat.App.1981), holding that a challenge to satisfaction of the best mode requirement could be raised against an application in interference, the Magdos and Kooi filed motions for reconsideration of the board's decision here, urging the board to consider whether the application on which Peltzer's patent issued satisfied the best mode requirement of Sec. 112.  On reconsideration, the board supplemented its original decision and concluded that, while it had jurisdiction to consider that issue, Peltzer had complied with Sec. 112.  The opinion on rehearing with respect to Interference No. 98,427, which is identical to that in Interference No. 98,428, appears at 212 USPQ 838.


30
We agree with the board that the assertions with respect to inoperability were clearly untimely, especially in view of the Magdos' own admission that those in the art were long aware of the problem.  Further, recasting the challenge into best mode terminology does not obviate the untimeliness of those assertions.    Cf. Department of Energy v. Daugherty, supra.

C.

31
Contrary to the board's view, Tofe v. Winchell, supra, does not answer the question whether a challenge to satisfaction of the best mode requirement may be raised against a patent in interference.   Compare Department of Energy v. Daugherty, 687 F.2d at 447, 215 USPQ at 12 (Nies, J., dissenting).  That question was not before the Court of Customs and Patent Appeals in Tofe and is also not properly before us in these appeals.  We agree with the board's original conclusion that the challenges made in these interferences were untimely.  Thus, whether a best mode challenge is ancillary to priority is irrelevant in these proceedings and we do not endorse either position of the board.  The supplemental decisions in Interference Nos. 98,427 and 98,428 which address only this issue are vacated.


32
The board's decisions awarding priority to Peltzer in Interference Nos. 98,427 and 98,428 and to Kooi in Interference No. 99,248 are affirmed.


33
AFFIRMED IN PART;  VACATED IN PART.



1
 Application Serial No. 290,586 entitled "Dielectric Isolation for High Density Semiconductor Devices," assigned to International Business Machines Corp


2
 Application Serial No. 150,609.  The involved application is a divisional application of this application


3
 Application Serial No. 160,650 entitled "Semiconductor Device, in Particular a Monolithic Integrated Circuit, and Method of Manufacturing the Same," assigned to North American Philips Co


4
 Dutch Application No. 7010204


5
 Application Serial No. 111,956 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure," assigned to Fairchild Camera and Instrument Corp


6
 Application Serial No. 187,124, filed October 6, 1971


7
 Application Serial No. 457,731 entitled "Integrated Circuit Structure with Oxidized Isolation," filed April 5, 1974


8
 For a brief introduction to IC fabrication, see J. Millman and C. Halkias, Integrated Circuits:  Analog and Digital Circuits and Systems at Sec. 7-2 (1972).   See also Noyce v. Kilby, 416 F.2d 1391, 163 USPQ 550 (Cust. & Pat.App.1969), cert. denied, 400 U.S. 818, 91 S.Ct. 34, 27 L.Ed.2d 45 (1970).  See In re Oguie, 517 F.2d 1382, 186 USPQ 227 (Cust. & Pat.App.1975), for a case discussing back to back PN junction isolation


9
 
The sole count of Interference No. 98,427:
A silicon structure comprising:  a semiconductor silicon substrate;  a semiconductor silicon expitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface;  and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer, said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed of oxidized portions of silicon material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer;  and wherein each pocket of epitaxial simiconductor [sic] material contains selected regions of differing conductivity type;  and including regions of low resistivity formed in the underlying substrate to interconnect regions separated by oxidized isolation regions.
The counts of Interference No. 98,428:
[Peltzer patent claims 1 and 7 from which the counts depend are:


1
 A silicon structure comprising:
a semiconductor silicon substrate;
a semiconductor silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface;  and
a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer;
said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed of oxidized portions of silicon material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer.


7
 Structure as in claim 1 wherein said substrate is of one type of conductivity and said epitaxial layer is of the opposite type conductivity.]
Count 1. Structure as in claim 7 including a low resistivity first region of opposite conductivity type formed in said substrate adjacent to said epitaxial layer of semiconductor material, and
a low resistivity second region of opposite conductivity type, said second region extending from the surface of said epitaxial layer into contact with said low resistivity first region, said second region being surrounded by an annular-shaped oxidized isolation region extending through said epitaxial layer to said first region in said substrate.
Count 2. Structure as in count 1 wherein said first region extends underneath a portion of said oxidized isolation region and into contact with another adjacent region of epitaxial silicon.
Count 3. Structure as in count 1 wherein said adjacent region of epitaxial silicon comprises:
a collector region of opposite conductivity type contacting said first region;
a base region of one conductivity type extending to the annular-shaped oxidized isolation region surrounding said adjacent region of epitaxial silicon;  and
an emitter region formed of opposite conductivity type in said base region.
The sole count of Interference No. 99,248:
A silicon structure comprising:  a semiconductor silicon substrate;  a semiconductor silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface, and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer;  said epitaxial layer comprising epitaxial silicon pockets laterally spaced from each other, each pocket of epitaxial semiconductor material containing selected regions of differing conductivity types;  and annular shaped regions formed of thermally oxidized portions of said epitaxial silicon layer surrounding each pocket, said annular shaped regions extending at least to said isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular shaped regions being substantially co-planar with the top surface of said epitaxial layer;  and regions of low resistivity formed in the underlying substrate to interconnect pockets separated by thermally oxidized isolation regions.


10
 Various isolation techniques are discussed in D. Hamilton and W. Howard, Basic Integrated Circuit Engineering (1975) at Chap. 3-1


11
 The epi is actually etched away in these regions and oxide is grown in these etched away areas


12
 35 U.S.C. Sec. 112, first paragraph (1976) provides, in pertinent part:
The specification ... shall set forth the best mode contemplated by the inventor of carrying out his invention.


13
 Channeling results in an electrical pathway just under the oxide layer which can defeat the isolation intended to be provided by the oxide


